Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: nust_logo                                                                                Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: image010                                                             Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: msu_logo_pos

   Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: C:\D Drive\CV and Website\10Oct11\index_files\Line.gif

 

 

 

 

Home

 

Bio Sketch

 

Teaching

 

Research

 

 

 

Embedded System Design

Course Code:

EE-430

Semester:

7th

Credit Hours:

3+1

Prerequisite Codes:

EE 241 Digital Logic Design(3+1)

Instructor:

 

Class:

BEE

Office:

 

Telephone:

 

Lecture Days:

 

E-mail:

 

Class Room:

 

Consulting Hours:

 

Knowledge Group:

Digital Systems & Signal Processing

Updates on LMS:

 

 

Course Description:

 

In today's world, embedded systems are everywhere -- homes, offices, cars, factories, hospitals, planes and consumer electronics. Their huge numbers and new complexity call for a new design approach, one that emphasizes high-level tools and hardware/software tradeoffs, rather than low-level assembly-language programming and logic design. This course presents the traditionally distinct fields of software and hardware design in a new unified approach. It covers trends and challenges, introduces the design and use of single-purpose processors ("hardware") and general-purpose processors ("software"), describes memories and buses, and illustrates hardware/software tradeoffs, chip technologies, and modern design tools.

 

Course Objectives:

 

The objective of this course is to enable the students to describe, evaluate and design embedded systems of various complexities. The students should feel confident building their own solutions based on modeling techniques and verify the functionality using industry tools.

 

Course Learning Outcomes (CLOs):

 

 

At the end of the course the students will be able to:

PLO

BT  Level*

 

1.       Describe the basic concepts of the Embedded System Design and shall be able to differentiate between the hardware and software viewpoints.

3

C-2, 3, 4

 

2.       List, recall and Use the various design techniques for single-purpose, general purpose and standard single purpose processors

5

C-1, 2, 3, 4

 

3.       Design various embedded systems while choosing the most optimal processor technology

3

C-4, 5, 6

 

4.       List & Describe various State machine and concurrent process models, evaluate their strengths and weaknesses and analyze their problems

3

C-1, 2, 3, 6

 

5.       Design an embedded system to solve a real-world problem that is not using embedded system technology in the local setting

5, 9

C-6, P-1, 3

 

* BT= Bloom’s Taxonomy, C=Cognitive domain, P=Psychomotor domain, A= Affective domain

 

 

 

 

Mapping of CLOs to Program Learning Outcomes

 

PLOs/CLOs

CLO1

CLO2

CLO3

CLO4

CLO5

PLO 1 (Engineering Knowledge)

 

 

 

 

 

PLO 2 (Problem Analysis)

 

 

 

 

 

PLO 3 (Design/Development of Solutions)

 

 

PLO 4 (Investigation)

 

 

 

 

 

PLO 5 (Modern tool usage)

 

 

 

PLO 6 (The Engineer and Society)

 

 

 

 

 

PLO 7 (Environment and Sustainability)

 

 

 

 

 

PLO 8 (Ethics)

 

 

 

 

 

PLO 9 (Individual and Team Work)

 

 

 

 

PLO 10 (Communication)

 

 

 

 

 

PLO 11 (Project Management)

 

 

 

 

 

PLO 12 (Lifelong Learning)

 

 

 

 

 

 

Mapping of CLOs to Assessment Modules and Weightages  (In accordance with NUST statutes)

                                                                                                              To be filled in at the end of the course.

Assessments/CLOs

CLO1

CLO2

CLO3

CLO4

CLO5

Quizzes: 12%

Assignments: 8%

OHT-1: 11%

OHT-2: 11%

Labs:15%

Project: 10%

 

 

 

 

 

End Semester Exam:33%

Total : 100 %

 

Books:

Text Book:

1.      Embedded System Design: A unified Hardware/Software Introduction, Frank Vahid and Tony Givargis, 2002.

2.      Introduction to Embedded Systems: A Cyber-Physical Systems Approach, E.A. Lee and S.A. Seshia, 2011.

Reference Books:

1.      Embedded Systems Design, Steve Heath, 2003

2.      Computer as Components, Wayne Wolf, 2005

 

Topics to be Covered:

 

1.       Introduction to Embedded Systems

 

2.       Custom Single Purpose Processors

 

3.       General Purpose Processors

 

4.       Standard Single Purpose Processors

 

5.       Memory

 

6.       Interfacing

 

7.       State Machine and Concurrent Process Models

 

8.       Modeling Dynamic Behaviors

 

9.       Analysis and Verification

 

 

Lecture Breakdown:

 

Week No.

Topics

Sections

Remarks

 

1

Lecture 1: Introduction to Embedded Systems

Lecture 2: Introduction to Embedded Systems

Lecture 3: Introduction to Embedded Systems

Vahid & Givargis 1.1

Vahid & Givargis 1.2-1.3

Vahid & Givargis 1.4-1.5

 

 

2

Lecture 4: Custom Single Purpose Processors

Lecture 5: Custom Single Purpose Processors

Lecture 6: Custom Single Purpose Processors

Lab 01: Implementation of Traffic Light Controller On 8051

Vahid & Givargis 2.2-2.3

Vahid & Givargis 2.4

Vahid & Givargis 2.5

 

 

3

Lecture 7: Custom Single Purpose Processors

Lecture 8: General Purpose Processors

Lecture 9: General Purpose Processors

Lab 02: Behavioral and Structural modeling of 4 bit Ripple Carry Adder (RCA) on FPGA

Vahid & Givargis 2.6

Vahid & Givargis 3.2

Vahid & Givargis 3.3

 

 

4

Lecture 10: General Purpose Processors

Lecture 11: General Purpose Processors

Lecture 12: General Purpose Processors

Lab 03: Implementation of a Dynamic Traffic Light Controller on FPGA

Vahid & Givargis 3.4

Vahid & Givargis 3.5

Vahid & Givargis 3.6

 

 

5

Lecture 13: General Purpose Processors

Lecture 14: Standard Single Purpose Processors

Lecture 15: Standard Single Purpose Processors

Lab 04: FPGA Tester Using 8051 Microcontroller

Vahid & Givargis 3.7-3.8

Vahid & Givargis 4.2

Vahid & Givargis 4.3-4.4

 

 

6

OHT-1

 

7

Lecture 16: Standard Single Purpose Processors

Lecture 17: Standard Single Purpose Processors

Lecture 18: Standard Single Purpose Processors

Lab 05: PWM generation using AVR Microcontroller

Vahid & Givargis 4.5-4.6

Vahid & Givargis 4.7

Vahid & Givargis 4.8-4.9

 

 

8

Lecture 19: Memory

Lecture 20: Memory

Lecture 21: Memory

Lab 06: Implementation of a Calculator with PIC Microcontroller, Keypad and Alphanumeric LCD

Vahid & Givargis 5.2

Vahid & Givargis 5.3

Vahid & Givargis 5.3-5.4

 

 

 

9

Lecture 22: Memory

Lecture 23: Memory

Lecture 24: Interfacing

Lab 07: Serial Communication with PIC Controller

Vahid & Givargis 5.5

Vahid & Givargis 5.5

Vahid & Givargis 6.2

 

 

10

Lecture 25: Interfacing

Lecture 26: Interfacing

Lecture 27: Interfacing

Lab 08: Analog to Digital Conversion using PIC Controller

Vahid & Givargis 6.3

Vahid & Givargis 6.3

Vahid & Givargis 6.4

 

 

11

Lecture 28: Interfacing

Lecture 29: Interfacing

Lecture 30: Interfacing

Lab 09: Microblaze on FPGA

Vahid & Givargis 6.5

Vahid & Givargis 6.6-6.7

Vahid & Givargis 6.8

 

 

 

12

OHT-2

 

13

Lecture 31: Interfacing

Lecture 32: Interfacing

Lecture 33: Interfacing

Lab 10: Graphics on Microblaze

Vahid & Givargis 6.9

Vahid & Givargis 6.10

Vahid & Givargis 6.11

 

 

14

Lecture 34: State Machine and Concurrent Process Models

Lecture 35: State Machine and Concurrent Process Models

Lecture 36: State Machine and Concurrent Process Models

Lab 11: Advanced Imaging with Microblaze – 1

Vahid & Givargis 8.7

Vahid & Givargis 8.8

Vahid & Givargis 8.11

 

 

15

Lecture 37: State Machine and Concurrent Process Models

Lecture 38: State Machine and Concurrent Process Models

Lecture 39: State Machine and Concurrent Process Models

Lab 12: Advanced Imaging with Microblaze - 2

Vahid & Givargis 8.12

Vahid & Givargis 8.13

Vahid & Givargis 8.15-8.16

 

 

16

Lecture 40: Modeling Dynamic Behaviors

Lecture 41: Modeling Dynamic Behaviors

Lecture 42: Modeling Dynamic Behaviors

Project

Lee & Seshia 3.1-3.7

Lee & Seshia 2.1-2.5

Lee & Seshia 4.1-4.3

 

 

 

17

Lecture 43: Analysis and Verification

Lecture 44: Analysis and Verification

Lecture 45: Analysis and Verification

Project

Lee & Seshia 12.1-12.3

Lee & Seshia 13.1-13.6

Lee & Seshia 14.1-14.5

 

 

18

ESE

 

Tools / Software Requirement:

 

Sofware Tools: Xilinx v12.2, Modelsim, Proteus, Keil, MPLab. Hardware Tools: Virtex-5(ml507) evaluation platform, 89C51 micro-controller is required for practical work. The system administration has installed all the software in the lab.

 

Grading Policy:

Quiz Policy:

The quizzes will be unannounced and normally last for ten minutes. The question framed is to test the concepts involved in last few lectures. Number of quizzes that will be used for evaluation is at the instructor’s discretion.

Assignment Policy:

In order to develop comprehensive understanding of the subject, assignments will be given. Late assignments will not be accepted / graded. All assignments will count towards the total (No ‘best-of’ policy). The students are advised to do the assignment themselves. Copying of assignments is highly discouraged and violations will be dealt with severely by referring any occurrences to the disciplinary committee. The questions in the assignment are meant to be challenging to give students confidence and extensive knowledge about the subject matter and enable them to prepare for the exams.

Lab Conduct:

The labs will be conducted for three hours every week. A lab handout will be given in advance for study and analysis The lab handouts will also be placed on LMS. The students are to submit their results by giving a lab report at the end of lab for evaluation. One lab report per group will be required. However, students will also be evaluated by oral viva during the lab.

Plagiarism:

SEECS maintains a zero tolerance policy towards plagiarism. While collaboration in this course is highly encouraged, you must ensure that you do not claim other people’s work/ ideas as your own.  Plagiarism occurs when the words, ideas, assertions, theories, figures, images, programming codes of others are presented as your own work. You must cite and acknowledge all sources of information in your assignments.  Failing to comply with the SEECS plagiarism policy will lead to strict penalties including zero marks in assignments and referral to the academic coordination office for disciplinary action.

 

 

 

Last Updated 14th August 2014.