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Teaching
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Embedded System Design
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Course Code:
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EE-430
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Semester:
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7th
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Credit Hours:
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3+1
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Prerequisite Codes:
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EE
241 Digital Logic Design(3+1)
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Instructor:
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Class:
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BEE
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Office:
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Telephone:
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Lecture Days:
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E-mail:
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Class Room:
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Consulting Hours:
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Knowledge Group:
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Digital Systems & Signal Processing
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Updates on LMS:
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Course Description:
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In today's world, embedded systems are
everywhere -- homes, offices, cars, factories, hospitals, planes and consumer
electronics. Their huge numbers and new complexity call for a new design
approach, one that emphasizes high-level tools and hardware/software
tradeoffs, rather than low-level assembly-language programming and logic
design. This course presents the traditionally distinct fields of
software and hardware design in a new unified approach. It covers trends
and challenges, introduces the design and use of single-purpose
processors ("hardware") and general-purpose processors
("software"), describes memories and buses, and illustrates
hardware/software tradeoffs, chip technologies, and modern design tools.
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Course Objectives:
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The objective of this course is to enable
the students to describe, evaluate and design embedded systems of various
complexities. The students should feel confident building their own
solutions based on modeling techniques and verify the functionality using
industry tools.
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Course Learning Outcomes (CLOs):
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At the end of the
course the students will be able to:
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PLO
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BT
Level*
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1.
Describe the basic concepts of the Embedded System
Design and shall be able to differentiate between the hardware and
software viewpoints.
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3
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C-2, 3, 4
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2.
List, recall
and Use the various design techniques for single-purpose, general
purpose and standard single purpose processors
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5
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C-1, 2, 3, 4
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3.
Design various
embedded systems while choosing the most optimal processor technology
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3
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C-4, 5, 6
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4.
List & Describe
various State machine and concurrent process models, evaluate
their strengths and weaknesses and analyze their problems
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3
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C-1, 2, 3, 6
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5.
Design an embedded
system to solve a real-world problem that is not using embedded system
technology in the local setting
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5, 9
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C-6, P-1, 3
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* BT= Bloom’s Taxonomy, C=Cognitive domain,
P=Psychomotor domain, A= Affective domain
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Mapping of CLOs to
Program Learning Outcomes
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PLOs/CLOs
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CLO1
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CLO2
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CLO3
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CLO4
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CLO5
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PLO 1 (Engineering Knowledge)
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PLO 2 (Problem Analysis)
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PLO 3 (Design/Development of Solutions)
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√
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√
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√
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PLO 4 (Investigation)
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PLO 5 (Modern tool usage)
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√
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√
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PLO 6 (The Engineer and Society)
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PLO 7 (Environment and Sustainability)
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PLO 8 (Ethics)
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PLO 9 (Individual and Team Work)
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√
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PLO 10 (Communication)
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PLO 11 (Project Management)
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PLO 12 (Lifelong Learning)
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Mapping of CLOs to
Assessment Modules and Weightages
(In accordance with NUST statutes)
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To
be filled in at the end of the course.
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Assessments/CLOs
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CLO1
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CLO2
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CLO3
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CLO4
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CLO5
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Quizzes:
12%
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Assignments:
8%
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OHT-1:
11%
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OHT-2:
11%
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Labs:15%
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Project: 10%
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End
Semester Exam:33%
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Total
: 100 %
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Books:
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Text
Book:
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1. Embedded System Design: A unified
Hardware/Software Introduction, Frank Vahid and
Tony Givargis, 2002.
2. Introduction to Embedded Systems: A
Cyber-Physical Systems Approach, E.A. Lee and S.A. Seshia,
2011.
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Reference
Books:
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1.
Embedded
Systems Design, Steve Heath, 2003
2.
Computer as
Components, Wayne Wolf, 2005
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Topics to be Covered:
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1.
Introduction to Embedded Systems
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2.
Custom Single Purpose Processors
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3.
General Purpose Processors
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4.
Standard Single Purpose Processors
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5.
Memory
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6.
Interfacing
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7.
State Machine and Concurrent Process Models
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8.
Modeling Dynamic Behaviors
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9.
Analysis and Verification
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Lecture Breakdown:
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Week
No.
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Topics
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Sections
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Remarks
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1
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Lecture
1: Introduction to Embedded Systems
Lecture
2: Introduction to Embedded Systems
Lecture
3: Introduction to Embedded Systems
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Vahid & Givargis
1.1
Vahid & Givargis
1.2-1.3
Vahid & Givargis
1.4-1.5
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2
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Lecture
4: Custom Single Purpose Processors
Lecture
5: Custom Single Purpose Processors
Lecture
6: Custom Single Purpose Processors
Lab
01: Implementation of Traffic Light Controller On 8051
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Vahid & Givargis
2.2-2.3
Vahid & Givargis
2.4
Vahid & Givargis
2.5
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3
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Lecture
7: Custom Single Purpose Processors
Lecture
8: General Purpose Processors
Lecture
9: General Purpose Processors
Lab
02: Behavioral and Structural modeling of 4 bit Ripple Carry Adder (RCA)
on FPGA
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Vahid & Givargis
2.6
Vahid & Givargis
3.2
Vahid & Givargis
3.3
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4
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Lecture
10: General Purpose Processors
Lecture
11: General Purpose Processors
Lecture
12: General Purpose Processors
Lab
03: Implementation of a Dynamic Traffic Light Controller on FPGA
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Vahid & Givargis
3.4
Vahid & Givargis
3.5
Vahid & Givargis
3.6
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5
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Lecture
13: General Purpose Processors
Lecture
14: Standard Single Purpose Processors
Lecture
15: Standard Single Purpose Processors
Lab
04: FPGA Tester Using 8051 Microcontroller
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Vahid & Givargis
3.7-3.8
Vahid & Givargis
4.2
Vahid & Givargis
4.3-4.4
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6
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OHT-1
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7
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Lecture
16: Standard Single Purpose Processors
Lecture
17: Standard Single Purpose Processors
Lecture
18: Standard Single Purpose Processors
Lab
05: PWM generation using AVR Microcontroller
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Vahid & Givargis
4.5-4.6
Vahid & Givargis
4.7
Vahid & Givargis
4.8-4.9
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8
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Lecture
19: Memory
Lecture
20: Memory
Lecture
21: Memory
Lab
06: Implementation of a Calculator with PIC Microcontroller, Keypad and
Alphanumeric LCD
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Vahid & Givargis
5.2
Vahid & Givargis
5.3
Vahid & Givargis
5.3-5.4
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9
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Lecture
22: Memory
Lecture
23: Memory
Lecture
24: Interfacing
Lab
07: Serial Communication with PIC Controller
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Vahid & Givargis
5.5
Vahid & Givargis
5.5
Vahid & Givargis
6.2
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10
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Lecture
25: Interfacing
Lecture
26: Interfacing
Lecture
27: Interfacing
Lab
08: Analog to Digital Conversion using PIC Controller
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Vahid & Givargis
6.3
Vahid & Givargis
6.3
Vahid & Givargis
6.4
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11
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Lecture
28: Interfacing
Lecture
29: Interfacing
Lecture
30: Interfacing
Lab
09: Microblaze on FPGA
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Vahid & Givargis
6.5
Vahid & Givargis
6.6-6.7
Vahid & Givargis
6.8
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12
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OHT-2
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13
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Lecture
31: Interfacing
Lecture
32: Interfacing
Lecture
33: Interfacing
Lab
10: Graphics on Microblaze
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Vahid & Givargis
6.9
Vahid & Givargis
6.10
Vahid & Givargis
6.11
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14
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Lecture
34: State Machine and Concurrent Process Models
Lecture
35: State Machine and Concurrent Process Models
Lecture
36: State Machine and Concurrent Process Models
Lab
11: Advanced Imaging with Microblaze – 1
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Vahid & Givargis
8.7
Vahid & Givargis
8.8
Vahid & Givargis
8.11
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15
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Lecture
37: State Machine and Concurrent Process Models
Lecture
38: State Machine and Concurrent Process Models
Lecture
39: State Machine and Concurrent Process Models
Lab
12: Advanced Imaging with Microblaze - 2
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Vahid & Givargis
8.12
Vahid & Givargis
8.13
Vahid & Givargis
8.15-8.16
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16
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Lecture
40: Modeling Dynamic Behaviors
Lecture
41: Modeling Dynamic Behaviors
Lecture
42: Modeling Dynamic Behaviors
Project
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Lee
& Seshia 3.1-3.7
Lee
& Seshia 2.1-2.5
Lee
& Seshia 4.1-4.3
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17
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Lecture
43: Analysis and Verification
Lecture
44: Analysis and Verification
Lecture
45: Analysis and Verification
Project
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Lee & Seshia 12.1-12.3
Lee & Seshia 13.1-13.6
Lee & Seshia 14.1-14.5
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18
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ESE
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Tools / Software Requirement:
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Sofware Tools: Xilinx v12.2, Modelsim,
Proteus, Keil, MPLab.
Hardware Tools: Virtex-5(ml507) evaluation platform, 89C51
micro-controller is required for practical work. The system
administration has installed all the software in the lab.
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Grading Policy:
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Quiz
Policy:
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The quizzes will be unannounced and normally
last for ten minutes. The question framed is to test the concepts
involved in last few lectures. Number of quizzes that will be used for
evaluation is at the instructor’s discretion.
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Assignment
Policy:
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In order to develop comprehensive understanding
of the subject, assignments will be given. Late assignments will not be
accepted / graded. All assignments will count towards the total (No
‘best-of’ policy). The students are advised to do the assignment
themselves. Copying of assignments is highly discouraged and violations
will be dealt with severely by referring any occurrences to the
disciplinary committee. The questions in the assignment are meant to be
challenging to give students confidence and extensive knowledge about the
subject matter and enable them to prepare for the exams.
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Lab
Conduct:
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The labs will be conducted for three
hours every week. A lab handout will be given in advance for study and
analysis The lab handouts will also be placed on LMS. The students are to
submit their results by giving a lab report at the end of lab for
evaluation. One lab report per group will be required. However, students
will also be evaluated by oral viva during the lab.
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Plagiarism:
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SEECS maintains a zero tolerance policy
towards plagiarism. While collaboration in this course is highly
encouraged, you must ensure that you do not claim other people’s work/
ideas as your own. Plagiarism
occurs when the words, ideas, assertions, theories, figures, images,
programming codes of others are presented as your own work. You must cite
and acknowledge all sources of information in your assignments. Failing to comply with the SEECS
plagiarism policy will lead to strict penalties including zero marks in
assignments and referral to the academic coordination office for
disciplinary action.
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